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riscv-mcu logoe203_hbirdv2

The Ultra-Low Power RISC-V Core

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Top Related Projects

1,103

Source files for SiFive's Freedom platforms

1,331

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

A FPGA friendly 32 bit RISC-V CPU implementation

SonicBOOM: The Berkeley Out-of-Order Machine

Quick Overview

The e203_hbirdv2 repository is an open-source project for the E203 RISC-V core, specifically tailored for the HBird V2 SoC (System on Chip). It provides a complete RTL implementation of the E203 core, along with associated documentation and tools for FPGA-based development and testing.

Pros

  • Fully open-source RISC-V core implementation
  • Designed for low-power and area-efficient applications
  • Includes comprehensive documentation and user guides
  • Supports FPGA-based development and testing

Cons

  • Limited to specific RISC-V instruction set extensions
  • May require specialized knowledge in RISC-V architecture and FPGA development
  • Documentation might be challenging for beginners
  • Potential compatibility issues with some third-party tools

Getting Started

To get started with the e203_hbirdv2 project:

  1. Clone the repository:

    git clone https://github.com/riscv-mcu/e203_hbirdv2.git
    
  2. Install required tools (Xilinx Vivado for FPGA development, RISC-V GNU Toolchain for software development)

  3. Follow the documentation in the doc directory for detailed setup and usage instructions

  4. Use the provided scripts in the fpga directory to generate bitstreams for supported FPGA boards

  5. Explore the software directory for example programs and demos

For more detailed instructions, refer to the project's README and documentation files.

Competitor Comparisons

1,103

Source files for SiFive's Freedom platforms

Pros of freedom

  • More comprehensive SoC design with multiple core options (E31, E51)
  • Better documentation and community support
  • Includes additional peripherals and features for a complete system

Cons of freedom

  • Higher complexity, potentially steeper learning curve
  • May require more resources to synthesize and implement

Code comparison

e203_hbirdv2:

module e203_core(
  input  clk,
  input  rst_n,
  // Other ports...
);
  // Core implementation
endmodule

freedom:

module rocket_core #(
  parameter XLen = 64
)(
  input         clock,
  input         reset,
  // Other ports...
);
  // Core implementation
endmodule

The freedom project uses parameterized designs, allowing for more flexibility in core configuration. e203_hbirdv2 focuses on a specific implementation, which may be simpler for beginners to understand and modify.

Both projects provide valuable RISC-V implementations, with e203_hbirdv2 offering a more focused, lightweight design suitable for MCU applications, while freedom provides a more comprehensive SoC platform with greater flexibility and features.

1,331

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Pros of ibex

  • More comprehensive documentation and user guides
  • Wider range of supported RISC-V extensions and features
  • Active development with frequent updates and contributions

Cons of ibex

  • Higher complexity and resource usage
  • Steeper learning curve for beginners
  • Less focus on MCU-specific optimizations

Code Comparison

e203_hbirdv2:

module e203_core(
  input  clk,
  input  rst_n,
  // Other ports...
);
  // Core implementation
endmodule

ibex:

module ibex_core #(
  parameter bit          PMPEnable         = 1'b0,
  parameter int unsigned PMPGranularity    = 0,
  // Other parameters...
) (
  input  logic        clk_i,
  input  logic        rst_ni,
  // Other ports...
);
  // Core implementation
endmodule

The ibex core offers more configurable parameters and follows a more modular design approach, while e203_hbirdv2 has a simpler interface tailored for MCU applications.

A FPGA friendly 32 bit RISC-V CPU implementation

Pros of VexRiscv

  • Written in SpinalHDL, allowing for more flexible and modular design
  • Highly configurable with various optional features and extensions
  • Better documentation and examples for customization

Cons of VexRiscv

  • Steeper learning curve due to SpinalHDL usage
  • May require more resources for full feature set implementation

Code Comparison

VexRiscv (SpinalHDL):

class VexRiscv(config : VexRiscvConfig) extends Component {
  val io = new Bundle {
    val iBus = master(IBusSimplified(config.iBusConfig))
    val dBus = master(DBusSimplified(config.dBusConfig))
    //...
  }
  //...
}

e203_hbirdv2 (Verilog):

module e203_core(
  input  clk,
  input  rst_n,
  
  input  [`E203_HART_ID_W-1:0] core_mhartid,
  //...
);
  //...
endmodule

The VexRiscv code showcases its configurability through the VexRiscvConfig parameter, while e203_hbirdv2 uses a more traditional Verilog module definition. VexRiscv's SpinalHDL approach allows for more concise and flexible hardware description compared to e203_hbirdv2's Verilog implementation.

SonicBOOM: The Berkeley Out-of-Order Machine

Pros of riscv-boom

  • More advanced and powerful RISC-V core implementation
  • Supports out-of-order execution for improved performance
  • Highly configurable and scalable design

Cons of riscv-boom

  • Higher complexity and resource requirements
  • May be overkill for simpler embedded applications
  • Steeper learning curve for implementation and customization

Code Comparison

riscv-boom:

class BoomCore(implicit p: Parameters) extends BoomModule()(p)
  with HasBoomCoreParameters
  with HasL1ICacheBankedParameters
{
  val io = IO(new BoomCoreIO)
  // ... (complex core implementation)
}

e203_hbirdv2:

module e203_core(
  input  clk,
  input  rst_n,
  // ... (simpler core interface)
);
  // ... (simpler core implementation)
endmodule

The code snippets highlight the difference in complexity and implementation language between the two projects. riscv-boom uses Scala for a more flexible and parameterized design, while e203_hbirdv2 uses Verilog for a more straightforward implementation.

riscv-boom is better suited for high-performance applications requiring advanced features, while e203_hbirdv2 is more appropriate for simpler embedded systems with lower resource requirements. The choice between them depends on the specific project needs and available resources.

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README

Hummingbirdv2 E203 Core and SoC

Deploy Documentation

About

This repository hosts the project for open-source Hummingbirdv2 E203 RISC-V processor Core and SoC, it's developped and opensourced by Nuclei System Technology, the leading RISC-V IP and Solution company based on China Mainland.

This's an upgraded version of the project Hummingbird E203 maintained in SI-RISCV/e200_opensource, so we call it Hummingbirdv2 E203, and its architecture is shown in the figure below. hbirdv2

In this new version, we have following updates.

  • Add NICE(Nuclei Instruction Co-unit Extension) for E203 core, so user could create customized HW co-units with E203 core easily.
  • Integrate the APB interface peripherals(GPIO, I2C, UART, SPI, PWM) from PULP Platform into Hummingbirdv2 SoC, these peripherals are implemented in Verilog language, so it's easy for user to understand.
  • Add new development boards(Nuclei ddr200t and mcu200t) support for Hummingbirdv2 SoC.

Welcome to visit https://github.com/riscv-mcu/hbird-sdk/ to use software development kit for the Hummingbird E203.

Welcome to visit https://www.rvmcu.com/community.html to participate in the discussion of the Hummingbird E203.

Welcome to visit http://www.rvmcu.com/ for more comprehensive information of availiable RISC-V MCU chips and embedded development.

Detailed Introduction and Quick Start-up

We have provided very detailed introduction and quick start-up documents to help you ramping it up.

The detailed introduction and the quick start documentation can be seen from https://doc.nucleisys.com/hbirdv2/.

By following the guidences from the doc, you can very easily start to use Hummingbirdv2 E203 processor Core and SoC.

What are you waiting for? Try it out now!

Dedicated FPGA-Boards and JTAG-Debugger

In order to easy user to study RISC-V in a quick and easy way, we have made dedicated FPGA-Boards and JTAG-Debugger.

Nuclei ddr200t development board

DDR200T

Nuclei mcu200t development board

MCU200T

Hummingbird Debugger

Debugger

The detailed introduction and the relevant documentation can be seen from https://nucleisys.com/developboard.php.

HummingBird SDK

Click https://github.com/riscv-mcu/hbird-sdk for software development kit.

Release History

Notice

  • Many people asked if this core and SoC can be commercially used, the answer as below:
    • According to the Apache 2.0 license, this open-sourced core can be used in commercial way.
    • But the feature is not full.
    • The main purpose of this open-sourced core is to be used by students/university/research/ and entry-level-beginners, hence, the commercial quality (bug-free) and service of this core is not not not warranted!!!

Release 0.2.1, Feb 26, 2021

This is release 0.2.1 of Hummingbirdv2.

  • Hbirdv2 SoC

    • Covert the peripheral IPs implemented in system verilog to verilog implementation.
  • SIM

    • Add new simulation tool(iVerilog) and wave viewer(GTKWave) support for Hummingbirdv2 SoC

Release 0.1.2, Nov 20, 2020

This is release 0.1.2 of Hummingbirdv2.

  • Hbirdv2 SoC

    • Remove unused module
    • Add one more UART
  • FPGA

    • Add new development board(Nuclei mcu200t) support for Hummingbirdv2 SoC

Release 0.1.1, Jul 28, 2020

This is release 0.1.1 of Hummingbirdv2.

NOTE:

  • This's an upgraded version of the project Hummingbird E203 maintained in SI-RISCV/e200_opensource.
  • Here are the new features of this release.
    • Add NICE(Nuclei Instruction Co-unit Extension) for E203 core
    • Integrate the APB interface peripherals(GPIO, I2C, UART, SPI, PWM) from PULP Platform
    • Add new development board(Nuclei ddr200t) support for Hummingbirdv2 SoC.