rocket-chip

Rocket Chip Generator

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Quick Overview

Rocket Chip is an open-source System on Chip (SoC) design generator, primarily focused on RISC-V based systems. It provides a flexible framework for creating customizable and extensible chip designs, allowing researchers and developers to experiment with various architectural features and configurations.

Pros

Highly configurable and extensible SoC design generator
Based on the open RISC-V instruction set architecture
Supports a wide range of customizations and optimizations
Active community and ongoing development

Cons

Steep learning curve for newcomers to hardware design
Documentation can be sparse or outdated in some areas
Requires significant computational resources for large designs
Limited support for commercial EDA tools

Code Examples

// Example 1: Defining a custom RocketCore configuration
class MyCustomCore(implicit p: Parameters) extends RocketCore()(p) {
  override lazy val dcache = Module(new DCacheModule()(p))
  override lazy val icache = Module(new ICacheModule()(p))
}

This example shows how to create a custom RocketCore configuration by overriding the default cache modules.

// Example 2: Adding a custom instruction to the decoder
class MyCustomRocketCore(implicit p: Parameters) extends RocketCore()(p) {
  override lazy val decode = new DecodeUnit {
    val custom_insn = BitPat("b????????????????_?????_?????_???_?????_???????")
    val custom_fn = FN_ADD
    val table = DecodeLogic(io.inst, default, Seq(
      custom_insn -> List(custom_fn, Y, N, N, N, N, N, N, N, N)
    ))
  }
}

This example demonstrates how to add a custom instruction to the decoder in a RocketCore.

// Example 3: Configuring a Rocket chip with custom parameters
class MyConfig extends Config((site, here, up) => {
  case XLen => 64
  case MaxHartIdBits => 4
  case RocketTilesKey => List(
    RocketTileParams(
      core = RocketCoreParams(fpu = Some(FPUParams())),
      dcache = Some(DCacheParams(nSets = 64, nWays = 4, rowBits = 128)),
      icache = Some(ICacheParams(nSets = 64, nWays = 4, rowBits = 128))
    )
  )
})

This example shows how to create a custom configuration for a Rocket chip, specifying parameters such as XLen, number of cores, and cache configurations.

Getting Started

To get started with Rocket Chip:

Clone the repository:

git clone https://github.com/chipsalliance/rocket-chip.git
cd rocket-chip

Install dependencies (assuming Ubuntu/Debian):

sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev

Build the project:

git submodule update --init --recursive
make

Run tests:
```
make test
```

For more detailed instructions and advanced usage, refer to the project's documentation and wiki on GitHub.

Competitor Comparisons

chipyard

1,563

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Pros of Chipyard

More comprehensive SoC design framework, including tools for simulation, FPGA prototyping, and ASIC flows
Easier to use and configure, with better documentation and examples
Supports a wider range of RISC-V cores and accelerators

Cons of Chipyard

Larger and more complex codebase, potentially harder to understand for beginners
May have higher resource requirements for simulation and synthesis
Slower development cycle due to its broader scope

Code Comparison

Rocket Chip (build.sbt):

lazy val commonSettings = Seq(
  organization := "edu.berkeley.cs",
  version := "1.2",
  scalaVersion := "2.12.4",
  traceLevel := 15,
  scalacOptions ++= Seq("-deprecation","-unchecked"),
  parallelExecution in Global := false
)

Chipyard (build.sbt):

lazy val commonSettings = Seq(
  organization := "edu.berkeley.cs",
  version := "1.6.0",
  scalaVersion := "2.12.10",
  traceLevel := 15,
  scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"),
  libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.0" % "test"
)

Both projects use SBT for build management, but Chipyard has a more recent Scala version and includes additional dependencies for testing.

riscv-boom

1,678

SonicBOOM: The Berkeley Out-of-Order Machine

Pros of riscv-boom

More advanced out-of-order execution, potentially offering higher performance
Designed for scalability, supporting multiple core configurations
Includes advanced features like branch prediction and speculative execution

Cons of riscv-boom

Higher complexity and resource requirements compared to Rocket Chip
Potentially longer development and verification cycles
May have a steeper learning curve for new users

Code Comparison

rocket-chip (simplified core instantiation):

class RocketTile(
  params: RocketTileParams,
  crossing: RocketCrossingParams
)(implicit p: Parameters) extends BaseTile(params, crossing)(p)
  with HasRocketCore
  with HasICacheFrontend
  with HasTileInputConstants

riscv-boom (simplified core instantiation):

class BoomTile(
  params: BoomTileParams,
  crossing: RocketCrossingParams
)(implicit p: Parameters) extends BaseTile(params, crossing)(p)
  with HasBoomCore
  with HasBoomICacheFrontend
  with HasTileInputConstants

Both projects use similar Chisel-based design patterns, but riscv-boom implements more complex out-of-order execution logic within its core components.

ibex

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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Pros of Ibex

Simpler and more lightweight design, suitable for embedded systems and IoT applications
Better documentation and easier to understand for newcomers to RISC-V
More focused on security features, including side-channel attack resistance

Cons of Ibex

Less powerful and feature-rich compared to Rocket Chip
Limited to 32-bit architecture, while Rocket Chip supports 64-bit
Smaller community and ecosystem around the project

Code Comparison

Ibex (RISC-V control logic):

always_comb begin
  illegal_insn = 1'b0;
  illegal_insn_o = 1'b0;
  case (opcode)
    OPCODE_LOAD:  illegal_insn = illegal_insn | illegal_insn_lsu;
    OPCODE_STORE: illegal_insn = illegal_insn | illegal_insn_lsu;
    // ... more cases
  endcase
end

Rocket Chip (RISC-V control logic):

class CtrlModule(implicit p: Parameters) extends Module {
  val io = IO(new Bundle {
    val imem = new FrontendIO
    val dmem = new HellaCacheIO
    val ptw = new TLBPTWIO
    // ... more IO definitions
  })
  // ... control logic implementation
}

The code snippets show different approaches to implementing RISC-V control logic. Ibex uses Verilog with a more straightforward case statement, while Rocket Chip employs Scala for a more complex and modular design.

VexRiscv

2,400

A FPGA friendly 32 bit RISC-V CPU implementation

Pros of VexRiscv

Written in SpinalHDL, offering more flexibility and easier customization
Highly configurable, with options for different pipeline stages and features
Better documentation and examples for getting started

Cons of VexRiscv

Less mature ecosystem compared to Rocket Chip
Smaller community and fewer resources for advanced implementations
Limited support for some advanced RISC-V extensions

Code Comparison

VexRiscv configuration example:

val config = VexRiscvConfig(
  plugins = List(
    new IBusCachedPlugin(
      resetVector = 0x80000000l,
      prediction = STATIC
    ),
    new DBusSimplePlugin(
      catchAddressMisaligned = false,
      catchAccessFault = false
    ),
    new DecoderSimplePlugin(
      catchIllegalInstruction = false
    ),
    new RegFilePlugin(
      regFileReadyKind = plugin.SYNC,
      zeroBoot = false
    ),
    new IntAluPlugin,
    new SrcPlugin(
      separatedAddSub = false,
      executeInsertion = true
    ),
    new FullBarrelShifterPlugin,
    new HazardSimplePlugin(
      bypassExecute = true,
      bypassMemory = true,
      bypassWriteBack = true,
      bypassWriteBackBuffer = true,
      pessimisticUseSrc = false,
      pessimisticWriteRegFile = false,
      pessimisticAddressMatch = false
    ),
    new BranchPlugin(
      earlyBranch = false,
      catchAddressMisaligned = false
    ),
    new YamlPlugin("cpu0.yaml")
  )
)

Rocket Chip configuration example:

class SmallConfig extends Config(
  new WithNSmallCores(1) ++
  new BaseConfig
)

class MediumConfig extends Config(
  new WithNBigCores(1) ++
  new BaseConfig
)

class LargeConfig extends Config(
  new WithNBigCores(4) ++
  new WithNMemoryChannels(2) ++
  new WithNBanks(8) ++
  new BaseConfig
)

freedom

1,103

Source files for SiFive's Freedom platforms

Pros of Freedom

More comprehensive SoC design platform, including board support packages
Includes additional tools and utilities for FPGA development
Better documentation and getting started guides for newcomers

Cons of Freedom

Larger and more complex codebase, potentially harder to navigate
May include proprietary components, limiting some usage scenarios
Less frequently updated compared to Rocket Chip

Code Comparison

Rocket Chip (Chisel):

class RocketTile(
    params: RocketTileParams,
    crossing: ClockCrossingType)
    (implicit p: Parameters) extends BaseTile(params, crossing)(p)
    with HasRocketCore
    with HasICacheFrontend
    with HasTileInputConstants

Freedom (Chisel):

class FreedomU500VC707DevKit()(implicit p: Parameters) extends ChipDevKit {
  override lazy val module = new FreedomU500VC707DevKitModule(this)
  val chipId = Some("freedom-u500-vc707")
  val resetCtrl = Some(new DevKitResetCtrl)
}

Both repositories use Chisel for hardware description, but Freedom focuses more on complete SoC designs and FPGA implementations, while Rocket Chip is more centered around the core RISC-V implementations and generator infrastructure.

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README

Rocket Chip Generator :rocket:

This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core. For more information on Rocket Chip, please consult our technical report.

RocketChip Dev Meeting

RocketChip development meetings happen every 2 weeks on Wednesday 17:00 â 18:00am CST (Pacific Time - Los Angeles) with meeting notes here:

Click here to subscribe Meeting Schedule(iCal format)
Click here to view Meeting Schedule via Google Calendar
Click here to join Zoom meeting (ID: 93899365000, passcode: 754340)

For possible time adjustments, they will be negotiated in Slack and published in the calendar.

Quick instructions for those who want to dive directly into the details without knowing exactly what's in the repository.
What's in the Rocket chip generator repository?
How should I use the Rocket chip generator?
How can I parameterize my Rocket chip?
Debugging with GDB
Building Rocket Chip with an IDE
Contributors

Quick Instructions

Checkout The Code

$ git clone https://github.com/ucb-bar/rocket-chip.git
$ cd rocket-chip
$ git submodule update --init

Install Necessary Dependencies

You may need to install some additional packages to use this repository. Rather than list all dependencies here, please see the appropriate section of the READMEs for each of the subprojects:

Building The Project

Generating verilog

$ make verilog

Generating verilog for a specific Config

$ make verilog CONFIG=DefaultSmallConfig

Keeping Your Repo Up-to-Date

If you are trying to keep your repo up to date with this GitHub repo, you also need to keep the submodules and tools up to date.

$ # Get the newest versions of the files in this repo
$ git pull origin master
$ # Make sure the submodules have the correct versions
$ git submodule update --init --recursive

If rocket-tools version changes, you should recompile and install rocket-tools according to the directions in the rocket-tools/README.

$ cd rocket-tools
$ ./build.sh
$ ./build-rv32ima.sh (if you are using RV32)

What's in the Rocket chip generator repository?

The rocket-chip repository is a meta-repository that points to several sub-repositories using Git submodules. Those repositories contain tools needed to generate and test SoC designs. This respository also contains code that is used to generate RTL. Hardware generation is done using Chisel, a hardware construction language embedded in Scala. The rocket-chip generator is a Scala program that invokes the Chisel compiler in order to emit RTL describing a complete SoC. The following sections describe the components of this repository.

Git Submodules

Git submodules allow you to keep a Git repository as a subdirectory of another Git repository. For projects being co-developed with the Rocket Chip Generator, we have often found it expedient to track them as submodules, allowing for rapid exploitation of new features while keeping commit histories separate. As submoduled projects adopt stable public APIs, we transition them to external dependencies. Here are the submodules that are currently being tracked in the rocket-chip repository:

chisel3 (https://github.com/ucb-bar/chisel3): The Rocket Chip Generator uses Chisel to generate RTL.
firrtl (https://github.com/ucb-bar/firrtl): Firrtl (Flexible Internal Representation for RTL) is the intermediate representation of RTL constructions used by Chisel3. The Chisel3 compiler generates a Firrtl representation, from which the final product (Verilog code, C code, etc) is generated.
hardfloat (https://github.com/ucb-bar/berkeley-hardfloat): Hardfloat holds Chisel code that generates parameterized IEEE 754-2008 compliant floating-point units used for fused multiply-add operations, conversions between integer and floating-point numbers, and conversions between floating-point conversions with different precision.
rocket-tools (https://github.com/freechipsproject/rocket-tools): We tag a version of RISC-V software tools that work with the RTL committed in this repository.
torture (https://github.com/ucb-bar/riscv-torture): This module is used to generate and execute constrained random instruction streams that can be used to stress-test both the core and uncore portions of the design.

Scala Packages

In addition to submodules that track independent Git repositories, the rocket-chip code base is itself factored into a number of Scala packages. These packages are all found within the src/main/scala directory. Some of these packages provide Scala utilities for generator configuration, while other contain the actual Chisel RTL generators themselves. Here is a brief description of what can be found in each package:

amba This RTL package uses diplomacy to generate bus implementations of AMBA protocols, including AXI4, AHB-lite, and APB.
config This utility package provides Scala interfaces for configuring a generator via a dynamically-scoped parameterization library.
coreplex This RTL package generates a complete coreplex by gluing together a variety of components from other packages, including: tiled Rocket cores, a system bus network, coherence agents, debug devices, interrupt handlers, externally-facing peripherals, clock-crossers and converters from TileLink to external bus protocols (e.g. AXI or AHB).
devices This RTL package contains implementations for peripheral devices, including the Debug module and various TL slaves.
diplomacy This utility package extends Chisel by allowing for two-phase hardware elaboration, in which certain parameters are dynamically negotiated between modules. For more information about diplomacy, see this paper.
groundtest This RTL package generates synthesizable hardware testers that emit randomized memory access streams in order to stress-tests the uncore memory hierarchy.
jtag This RTL package provides definitions for generating JTAG bus interfaces.
regmapper This utility package generates slave devices with a standardized interface for accessing their memory-mapped registers.
rocket This RTL package generates the Rocket in-order pipelined core, as well as the L1 instruction and data caches. This library is intended to be used by a chip generator that instantiates the core within a memory system and connects it to the outside world.
tile This RTL package contains components that can be combined with cores to construct tiles, such as FPUs and accelerators.
tilelink This RTL package uses diplomacy to generate bus implementations of the TileLink protocol. It also contains a variety of adapters and protocol converters.
system This top-level utility package invokes Chisel to elaborate a particular configuration of a coreplex, along with the appropriate testing collateral.
unittest This utility package contains a framework for generateing synthesizable hardware testers of individual modules.
util This utility package provides a variety of common Scala and Chisel constructs that are re-used across multiple other packages,

Other Resources

Outside of Scala, we also provide a variety of resources to create a complete SoC implementation and test the generated designs.

bootrom Sources for the first-stage bootloader included in the BootROM.
csrc C sources for use with Verilator simulation.
docs Documentation, tutorials, etc for specific parts of the codebase.
emulator Directory in which Verilator simulations are compiled and run.
regression Defines continuous integration and nightly regression suites.
scripts Utilities for parsing the output of simulations or manipulating the contents of source files.
vsim Directory in which Synopsys VCS simulations are compiled and run.
vsrc Verilog sources containing interfaces, harnesses and VPI.

IDEs Support

The Rocket Chip Scala build uses mill as build tool.

IDEs like IntelliJ and VSCode are popular in the Scala community and work with Rocket Chip.

The Rocket Chip currently uses nix to configure the build and/or development environment, you need to install it first depending on your OS distro.

Then follow the steps:

Generate BSP config by running:
```
mill mill.bsp.BSP/install
```

Patch the argv in .bsp/mill-bsp.json, from

{"name":"mill-bsp","argv":["/usr/bin/mill","--bsp","--disable-ticker","--color","false","--jobs","1"],"millVersion":"0.10.9","bspVersion":"2.0.0","languages":["scala","java"]}

{"name":"mill-bsp","argv":["/usr/bin/nix","develop","-c","mill","--bsp","--disable-ticker","--color","false","--jobs","1"],"millVersion":"0.10.9","bspVersion":"2.0.0","languages":["scala","java"]}

For IntelliJ users

Install and configure Scala plugin.
BSP should be automatically run. If it doesn't, click bsp on the right bar, then right-click on your project to reload.

For VSCode users

Install and configure Metals extension.
Execute VSCode command Metals: Import build.

Contributors

Contributing guidelines can be found in CONTRIBUTING.md.

A list of contributors can be found here.

Attribution

If used for research, please cite Rocket Chip by the technical report:

Krste AsanoviÄ, Rimas AviÅ¾ienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Palmer Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Benjamin Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo, and Andrew Waterman, The Rocket Chip Generator, Technical Report UCB/EECS-2016-17, EECS Department, University of California, Berkeley, April 2016

Top Related Projects

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Top Related Projects

Quick Overview

Pros

Cons

Code Examples

Getting Started

Competitor Comparisons

Pros of Chipyard

Cons of Chipyard

Code Comparison

Pros of riscv-boom

Cons of riscv-boom

Code Comparison

Pros of Ibex

Cons of Ibex

Code Comparison

Pros of VexRiscv

Cons of VexRiscv

Code Comparison

Pros of Freedom

Cons of Freedom

Code Comparison

Convert designs to code with AI

README

Rocket Chip Generator :rocket:

RocketChip Dev Meeting

Table of Contents

Quick Instructions

Checkout The Code

Install Necessary Dependencies

Building The Project

Keeping Your Repo Up-to-Date

What's in the Rocket chip generator repository?

Git Submodules

Scala Packages

Other Resources

IDEs Support

For IntelliJ users

For VSCode users

Contributors

Attribution

Top Related Projects

Convert designs to code with AI