chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

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Quick Overview

Chipyard is an integrated framework for designing and evaluating systems-on-chip (SoCs) based on the RISC-V instruction set architecture. It provides a comprehensive set of tools, generators, and libraries to facilitate the development of custom SoCs, from RTL design to FPGA implementation and software development.

Pros

Comprehensive ecosystem for RISC-V SoC design and evaluation
Highly customizable and extensible architecture
Supports multiple simulation and implementation targets (e.g., Verilator, VCS, FPGA)
Integrates with popular open-source hardware design tools and generators

Cons

Steep learning curve for newcomers to hardware design and RISC-V
Requires significant computational resources for large designs
Documentation can be sparse or outdated in some areas
Limited support for commercial EDA tools compared to traditional ASIC flows

Getting Started

To get started with Chipyard, follow these steps:

Clone the repository and initialize submodules:

git clone https://github.com/ucb-bar/chipyard.git
cd chipyard
./scripts/init-submodules-no-riscv-tools.sh

Install dependencies:

./scripts/build-toolchains.sh riscv-tools

Build the default simulator:
```
cd sims/verilator
make
```
Run a simple simulation:
```
make run-binary-hello
```

For more detailed instructions and advanced usage, refer to the official Chipyard documentation.

Competitor Comparisons

rocket-chip

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Rocket Chip Generator

Pros of Rocket Chip

More focused and lightweight, specifically targeting the RISC-V Rocket core
Longer history and potentially more stable codebase
Easier to integrate into custom SoC designs due to its modular nature

Cons of Rocket Chip

Less comprehensive tooling and simulation infrastructure
Narrower scope, primarily focused on the Rocket core rather than a full SoC environment
May require more manual configuration and setup for complex designs

Code Comparison

Rocket Chip (configuration example):

class MyConfig extends Config(
  new WithNBigCores(1) ++
  new WithNSmallCores(2) ++
  new BaseConfig)

Chipyard (configuration example):

class MyConfig extends Config(
  new WithTop(new MyTop(_)) ++
  new WithBootROM ++
  new freechips.rocketchip.system.BaseConfig)

Both projects use Chisel for hardware description, but Chipyard provides a more comprehensive framework for SoC design and simulation. Rocket Chip focuses on the core implementation, while Chipyard builds upon it to offer a full-featured SoC development environment with additional tools and integrations.

opentitan

2,496

OpenTitan: Open source silicon root of trust

Pros of OpenTitan

Focuses on secure hardware design, including a secure root of trust
Provides a complete system-on-chip (SoC) design with various IP blocks
Emphasizes open-source hardware development and collaboration

Cons of OpenTitan

More specialized focus on security, potentially less flexible for general-purpose designs
Steeper learning curve for those not familiar with secure hardware concepts
May have fewer readily available tools for rapid prototyping compared to Chipyard

Code Comparison

OpenTitan (Verilog):

module aes_cipher_core (
  input              clk_i,
  input              rst_ni,
  input              en_i,
  input  [3:0][31:0] state_i,
  output [3:0][31:0] state_o
);

Chipyard (Chisel):

class AES extends Module {
  val io = IO(new Bundle {
    val in = Input(Vec(4, UInt(32.W)))
    val out = Output(Vec(4, UInt(32.W)))
    val en = Input(Bool())
  })

Both repositories provide hardware design frameworks, but OpenTitan focuses on secure hardware development, while Chipyard offers a more general-purpose RISC-V based SoC design environment. The code snippets illustrate the different hardware description languages used: Verilog for OpenTitan and Chisel for Chipyard.

riscv-boom

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SonicBOOM: The Berkeley Out-of-Order Machine

Pros of riscv-boom

Focused specifically on RISC-V BOOM (Berkeley Out-of-Order Machine) processor implementation
Simpler and more lightweight repository structure
Easier to understand and contribute to for those primarily interested in BOOM

Cons of riscv-boom

Limited to BOOM processor, lacks broader SoC design capabilities
Fewer tools and utilities for chip design and verification
Less comprehensive documentation and tutorials

Code comparison

riscv-boom:

class BoomCore(implicit p: Parameters) extends CoreModule()(p)
  with HasBoomCoreParameters
  with HasBoomCSRFile {
  val io = IO(new BoomCoreIO)
  // Core implementation
}

Chipyard:

class ChipTop(implicit p: Parameters) extends System
  with HasPeripheryDebug
  with HasPeripheryBootROM
  with HasPeripherySerial
  with HasPeripheryUART
  with HasPeripheryIceNIC {
  override lazy val module = new ChipTopModule(this)
}

The riscv-boom code focuses on the BOOM core implementation, while Chipyard provides a more comprehensive SoC design with various peripherals and interfaces.

freedom

1,103

Source files for SiFive's Freedom platforms

Pros of Freedom

More focused on commercial RISC-V implementations
Provides a complete SoC design, including peripherals
Better documentation for hardware designers

Cons of Freedom

Less flexible for academic research purposes
Smaller community and ecosystem compared to Chipyard
Limited support for advanced features like out-of-order execution

Code Comparison

Freedom (SoC configuration):

class FreedomU500VC707DevKit extends Config(
  new WithNBreakpoints(2) ++
  new WithNBigCores(1) ++
  new WithRV32 ++
  new FreedomUVC707Config().alter((site,here,up) => {
    case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery bus
  })
)

Chipyard (SoC configuration):

class RocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
  new freechips.rocketchip.subsystem.WithRV32 ++
  new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
  new freechips.rocketchip.system.BaseConfig
)

Both repositories use Chisel for hardware description, but Freedom focuses on specific SoC designs while Chipyard provides a more flexible framework for customization and research.

riscv-isa-sim

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Spike, a RISC-V ISA Simulator

Pros of riscv-isa-sim

Focused specifically on RISC-V ISA simulation
Lightweight and easier to set up for basic RISC-V instruction testing
Provides a standalone RISC-V instruction set simulator (Spike)

Cons of riscv-isa-sim

Limited scope compared to Chipyard's full SoC design capabilities
Lacks advanced features for chip design and verification
Does not include RTL generation or FPGA support

Code Comparison

riscv-isa-sim (Spike simulator):

#include "riscv/sim.h"
#include "riscv/processor.h"

int main(int argc, char** argv) {
  sim_t sim(argc, argv);
  sim.run();
  return 0;
}

Chipyard (Rocket Chip generator):

class RocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
  new freechips.rocketchip.system.BaseConfig)

class Top extends RocketSubsystem
  with HasPeripheryDebug
  with HasSystemErrorSlave

The riscv-isa-sim code shows a simple C++ implementation of the Spike simulator, while the Chipyard code demonstrates Scala-based configuration for generating a Rocket Chip SoC. Chipyard offers more extensive customization options for chip design, whereas riscv-isa-sim focuses on instruction-level simulation.

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README

Chipyard Framework

Quick Links

Latest Documentation: https://chipyard.readthedocs.io/
User Question Forum: https://groups.google.com/forum/#!forum/chipyard
Bugs and Feature Requests: https://github.com/ucb-bar/chipyard/issues

Using Chipyard

To get started using Chipyard, see the documentation on the Chipyard documentation site: https://chipyard.readthedocs.io/

What is Chipyard

Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other Berkeley projects to produce a RISC-V SoC with everything from MMIO-mapped peripherals to custom accelerators. Chipyard contains processor cores (Rocket, BOOM, CVA6 (Ariane)), vector units (Saturn, Ara), accelerators (Gemmini, NVDLA), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation (FireSim), automated VLSI flows (Hammer), and software workload generation for bare-metal and Linux-based systems (FireMarshal). Chipyard is actively developed in the Berkeley Architecture Research Group in the Electrical Engineering and Computer Sciences Department at the University of California, Berkeley.

Resources

Chipyard Documentation: https://chipyard.readthedocs.io/
Chipyard (x FireSim) Tutorial: https://fires.im/tutorial-recent/
Chipyard Basics slides: https://fires.im/asplos23-slides-pdf/02_chipyard_basics.pdf

Need help?

Join the Chipyard Mailing List: https://groups.google.com/forum/#!forum/chipyard
If you find a bug or would like propose a feature, post an issue on this repo: https://github.com/ucb-bar/chipyard/issues

Contributing

See CONTRIBUTING.md

Attribution and Chipyard-related Publications

If used for research, please cite Chipyard by the following publication:

@article{chipyard,
  author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar,   Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanovi\'{c}, Krste and Nikoli\'{c}, Borivoje},
  journal={IEEE Micro},
  title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs},
  year={2020},
  volume={40},
  number={4},
  pages={10-21},
  doi={10.1109/MM.2020.2996616},
  ISSN={1937-4143},
}

Chipyard
- A. Amid, et al. IEEE Micro'20 PDF.
- A. Amid, et al. DAC'20 PDF.
- A. Amid, et al. ISCAS'21 PDF.

These additional publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs.

Generators
- Rocket Chip: K. Asanovic, et al., UCB EECS TR. PDF.
- BOOM: C. Celio, et al., Hot Chips 30. PDF.
  - SonicBOOM (BOOMv3): J. Zhao, et al., CARRV'20. PDF.
  - COBRA (BOOM Branch Prediction): J. Zhao, et al., ISPASS'21. PDF.
- Gemmini: H. Genc, et al., DAC'21. PDF.
Sims
- FireSim: S. Karandikar, et al., ISCA'18. PDF.
  - FireSim Micro Top Picks: S. Karandikar, et al., IEEE Micro, Top Picks 2018. PDF.
  - FASED: D. Biancolin, et al., FPGA'19. PDF.
  - Golden Gate: A. Magyar, et al., ICCAD'19. PDF.
  - FirePerf: S. Karandikar, et al., ASPLOS'20. PDF.
  - FireSim ISCA@50 Retrospective: S. Karandikar, et al., ISCA@50 Retrospective: 1996-2020. PDF
Tools
- Chisel: J. Bachrach, et al., DAC'12. PDF.
- FIRRTL: A. Izraelevitz, et al., ICCAD'17. PDF.
- Chisel DSP: A. Wang, et al., DAC'18. PDF.
- FireMarshal: N. Pemberton, et al., ISPASS'21. PDF.
VLSI
- Hammer: E. Wang, et al., ISQED'20. PDF.
- Hammer: H. Liew, et al., DAC'22. PDF.

Acknowledgements

This work is supported by the NSF CCRI ENS Chipyard Award #2016662.

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