cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

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Quick Overview

CVA6 is an open-source, 64-bit application class RISC-V processor core developed by OpenHW Group. It is designed to be configurable and extensible, suitable for various applications ranging from embedded systems to high-performance computing.

Pros

Fully compliant with RISC-V ISA specifications, ensuring compatibility and portability
Highly configurable, allowing users to tailor the core to specific application needs
Supports both 32-bit and 64-bit modes, providing flexibility for different use cases
Active community and ongoing development, ensuring continuous improvements and support

Cons

Relatively complex design compared to simpler RISC-V cores, which may increase implementation challenges
Documentation could be more comprehensive for easier adoption by new users
Limited commercial support compared to proprietary alternatives
Performance may not match high-end commercial processors in some applications

Code Examples

As CVA6 is a hardware design project and not a software library, there are no direct code examples to provide. However, here are some examples of how you might interact with or configure the CVA6 core using hardware description languages:

// Example: Instantiating the CVA6 core in a Verilog design
cva6 #(
    .XLEN(64),
    .FPGA_EN(1),
    .NUM_MHPMCOUNTERS(1)
) i_cva6 (
    .clk_i(clk),
    .rst_ni(rst_n),
    .boot_addr_i(32'h80000000),
    .hart_id_i(64'h0),
    // ... other ports
);

// Example: Configuring CVA6 parameters in SystemVerilog
localparam CVA6Cfg = '{
    XLEN: 64,
    FPGA_EN: 1,
    NUM_MHPMCOUNTERS: 1,
    RVFI: 0,
    CLIC: 1,
    // ... other parameters
};

Getting Started

To get started with CVA6:

Clone the repository:

git clone https://github.com/openhwgroup/cva6.git
cd cva6

Install required tools (Verilator, RISC-V GCC toolchain, etc.)
Build the simulation model:
```
make verilate
```
Run tests or simulate the core:
```
make run-tests
```

For detailed instructions, refer to the project's documentation and README files.

Competitor Comparisons

ibex

1,599

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Pros of Ibex

Simpler design, easier to understand and modify
Lower power consumption and smaller area footprint
More extensive documentation and user guides

Cons of Ibex

Lower performance compared to CVA6
Limited support for advanced features like out-of-order execution
Fewer configuration options and customization possibilities

Code Comparison

CVA6 (RISC-V 64-bit implementation):

always_comb begin : trap_ctrl
    trap_ctrl_n    = trap_ctrl_q;
    exception_n    = exception_q;
    exception_pc_n = exception_pc_q;
    // ... (more complex logic)
end

Ibex (RISC-V 32-bit implementation):

always_comb begin : exception_ctrl
    exception_ctrl_ns = exception_ctrl_cs;
    exc_cause_o       = exc_cause;
    exc_pc_o          = pc_id_i;
    // ... (simpler logic)
end

The code snippets demonstrate the difference in complexity between CVA6 and Ibex. CVA6's trap control logic is more intricate, reflecting its advanced features, while Ibex's exception control is more straightforward, aligning with its simpler design philosophy.

riscv-boom

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SonicBOOM: The Berkeley Out-of-Order Machine

Pros of RISCV-BOOM

More advanced out-of-order execution, potentially offering higher performance
Extensive configurability, allowing for a wide range of design points
Strong focus on research and education, with detailed documentation

Cons of RISCV-BOOM

Higher complexity and resource usage compared to CVA6
Potentially longer development cycles due to its more complex architecture
May require more effort to integrate into existing systems

Code Comparison

RISCV-BOOM (Fetch Stage):

class FetchBundle(implicit p: Parameters) extends BoomBundle
  val pc = UInt(vaddrBitsExtended.W)
  val edge_inst = Bool()
  val ftq_idx = UInt(log2Ceil(ftqSz).W)
  val mask = UInt((fetchWidth + 1).W)

CVA6 (Fetch Stage):

module cv32e40p_if_stage import cv32e40p_pkg::*; (
  input  logic        clk,
  input  logic        rst_n,
  input  logic        fetch_enable_i,
  output logic [31:0] fetch_addr_o,
  input  logic [31:0] fetch_rdata_i
);

Both repositories implement RISC-V processors, but RISCV-BOOM focuses on a more complex out-of-order design, while CVA6 aims for a simpler in-order implementation. The code snippets show differences in language (Scala vs. SystemVerilog) and complexity of the fetch stage implementation.

rocket-chip

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Pros of rocket-chip

More mature and widely adopted in academia and industry
Extensive ecosystem with tools and extensions (e.g., Chipyard)
Highly configurable and parameterizable design

Cons of rocket-chip

Steeper learning curve due to complex codebase and Chisel HDL
Less focus on commercial-grade features and verification
Slower release cycle and community engagement

Code Comparison

rocket-chip (Chisel):

class Rocket extends Module {
  val io = IO(new Bundle {
    val imem = new FrontendIO
    val dmem = new HellaCacheIO
    val ptw = new TLBPTWIO
    val fpu = new FPUCoreIO().flip
  })
  // ...
}

cva6 (SystemVerilog):

module cva6 import ariane_pkg::*; #(
  parameter int unsigned HART_ID = 0
) (
  input  logic                clk_i,
  input  logic                rst_ni,
  input  logic [63:0]         boot_addr_i,
  // ...
);
  // ...
endmodule

Both repositories implement RISC-V processors, but with different approaches. rocket-chip uses Chisel HDL and focuses on configurability, while cva6 uses SystemVerilog and emphasizes commercial-grade features. The code snippets show the different languages and module structures used in each project.

VexRiscv

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A FPGA friendly 32 bit RISC-V CPU implementation

Pros of VexRiscv

Written in SpinalHDL, allowing for more flexible and modular design
Highly configurable with various optional features and extensions
Supports a wider range of RISC-V extensions out of the box

Cons of VexRiscv

Less focus on high-performance implementations compared to CVA6
May require more effort to integrate into existing SystemVerilog-based projects
Documentation and community support might be less extensive

Code Comparison

VexRiscv (SpinalHDL):

class VexRiscv(config: VexRiscvConfig) extends Component {
  val io = new Bundle {
    val iBus = master(IBusSimplified(config.iBusConfig))
    val dBus = master(DBusSimplified(config.dBusConfig))
    //...
  }
  //...
}

CVA6 (SystemVerilog):

module cva6 import ariane_pkg::*; #(
  parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
) (
  input  logic                         clk_i,
  input  logic                         rst_ni,
  //...
);
  //...
endmodule

The code snippets showcase the different languages and design approaches used in each project. VexRiscv utilizes SpinalHDL's object-oriented style, while CVA6 employs traditional SystemVerilog module definitions.

freedom

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Source files for SiFive's Freedom platforms

Pros of Freedom

More comprehensive ecosystem with SoC designs and development boards
Better documentation and getting started guides
Wider industry adoption and commercial support from SiFive

Cons of Freedom

Less focus on academic/research use cases
More complex codebase due to broader scope
Potentially more challenging for newcomers to contribute

Code Comparison

CVA6:

module cva6 #(
  parameter int unsigned HART_ID = 0,
  parameter int unsigned NUM_WORDS = 2**25
) (
  input  logic        clk_i,
  input  logic        rst_ni,

Freedom:

class FreedomU500VC707DevKitConfig extends Config(
  new WithJtagDTM            ++
  new WithNMemoryChannels(1) ++
  new WithNBigCores(1)       ++
  new BaseConfig)

The CVA6 example shows a Verilog module definition, while Freedom uses Chisel/Scala for configuration. This reflects the different approaches: CVA6 is more traditional RTL, while Freedom leverages higher-level hardware description languages.

riscv-isa-sim

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Spike, a RISC-V ISA Simulator

Pros of riscv-isa-sim

Focuses on instruction set simulation, providing a comprehensive RISC-V ISA emulator
Offers a flexible and extensible framework for RISC-V software development and testing
Supports a wide range of RISC-V extensions and custom instructions

Cons of riscv-isa-sim

Limited in hardware design and implementation aspects
May not provide detailed timing and power analysis capabilities
Less suitable for hardware-specific optimizations and verification

Code Comparison

riscv-isa-sim (Spike):

void processor_t::step(size_t n)
{
  for (size_t i = 0; i < n; i++)
    step(1);
  update_histogram(n);
}

cva6:

always_ff @(posedge clk_i or negedge rst_ni) begin
    if (~rst_ni) begin
        pc_d <= RESET_VECTOR;
    end else begin
        pc_d <= pc_n;
    end
end

The riscv-isa-sim code shows a high-level simulation step, while cva6 demonstrates low-level hardware description for program counter updates.

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README

CVA6 RISC-V CPU

CVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore, it is compliant to the draft external debug spec 0.13.

It has a configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer and branch history table). The primary design goal was on reducing critical path length.

The CVA6 core is part of a vivid ecosystem. In this document, we gather pointers to this ecosystem (building blocks, designs, partners...).

A performance model of CVA6 is available in the perf-model/ folder of this repository. It can be used to investigate performance-related micro-architecture changes.

Quick setup

The following instructions will allow you to compile and run a Verilator model of the CVA6 APU (which instantiates the CVA6 core) within the CVA6 APU testbench (corev_apu/tb).

Throughout all build and simulations scripts executions, you can use the environment variable NUM_JOBS to set the number of concurrent jobs launched by make:

if left undefined, NUM_JOBS will default to 1, resulting in a sequential execution of make jobs;
when setting NUM_JOBS to an explicit value, it is recommended not to exceed 2/3 of the total number of virtual cores available on your system.

Checkout the repository and initialize all submodules.

git clone https://github.com/openhwgroup/cva6.git
cd cva6
git submodule update --init --recursive

Install the GCC Toolchain build prerequisites then the toolchain itself.

:warning: It is strongly recommended to use the toolchain built with the provided scripts.

Install cmake, version 3.14 or higher.
Set the RISCV environment variable.

export RISCV=/path/to/toolchain/installation/directory

Install help2man and device-tree-compiler packages.

For Debian-based Linux distributions, run :

sudo apt-get install help2man device-tree-compiler

Install the riscv-dv requirements:

pip3 install -r verif/sim/dv/requirements.txt

Run these commands to install a custom Spike and Verilator (i.e. these versions must be used to simulate the CVA6) and these tests suites.

# DV_SIMULATORS is detailed in the next section
export DV_SIMULATORS=veri-testharness,spike
bash verif/regress/smoke-tests.sh

Tutorials

Running Simulations
ASIC Implementation
FPGA Implementation and running an OS

Directory Structure

The directory structure separates the CVA6 RISC-V CPU core from the CORE-V-APU FPGA Emulation Platform. Files, directories and submodules under cva6 are for the core only and should not have any dependencies on the APU. Files, directories and submodules under corev_apu are for the FPGA Emulation platform. The CVA6 core can be compiled stand-alone, and obviously the APU is dependent on the core.

The top-level directories of this repo:

ci: Scriptware for CI.
common: Source code used by both the CVA6 Core and the COREV APU. Subdirectories from here are local for common files that are hosted in this repo and submodules that are hosted in other repos.
core: Source code for the CVA6 Core only. There should be no sources in this directory used to build anything other than the CVA6 core.
corev_apu: Source code for the CVA6 APU, exclusive of the CVA6 core. There should be no sources in this directory used to build the CVA6 core.
docs: Documentation.
pd: Example and CI scripts to synthesis CVA6.
util: General utility scriptware.
vendor: Third-party IP maintained outside the repository.
verif: Verification environment for the CVA6. The verification files shared with other cores are in the core-v-verif repository on GitHub. core-v-verif is defined as a cva6 submodule.

verif Directories

bsp: board support package for test-programs compiled/assembled/linked for the CVA6. This BSP is used by both core testbench and uvmt_cva6 UVM verification environment.
regress: scripts to install tools, test suites, CVA6 code and to execute tests
sim: simulation environment (e.g. riscv-dv)
tb: testbench module instancing the core
tests: source of test cases and test lists

Contributing

We highly appreciate community contributions. To ease the work of reviewing contributions, please review CONTRIBUTING.

Contributions to the documentation (docs/ and tutorials/ directories) are very welcome as well.

If you find any problems or issues with CVA6 or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.
The CVA6 Kanban Board loosely tracks planned improvements.

Publication

If you use CVA6 in your academic work you can cite us:

CVA6 Publication

@article{zaruba2019cost,
   author={F. {Zaruba} and L. {Benini}},
   journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
   title={The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology},
   year={2019},
   volume={27},
   number={11},
   pages={2629-2640},
   doi={10.1109/TVLSI.2019.2926114},
   ISSN={1557-9999},
   month={Nov},
}

Acknowledgements

Check out the acknowledgements.

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